1. Field of the Invention
The present invention relates to a variable delay circuit suitable for an LSI tester, and more particularly to a variable delay circuit improved in speed and accuracy.
2. Description of the Related Art
Recently, with the speed-up of semiconductor integrated circuits, there arises a demand for a more accurate LSI tester and there is an increase in the frequency to be dealt with. The performance of an LSI tester depends on the performance of a variable delay circuit integrated therewith.
FIG. 18 is a circuit diagram showing a conventional variable delay circuit. The conventional variable delay circuit is provided with two delay circuits DLY101 and DLY102 having the same structure. The delay circuit DLY101 comprises a ramp generator RG51, a comparator CP51 connected to the ramp generator RG51, an inverter IV51 connected to the comparator CP51, and a capacitive element C51 connected between the ramp generator RG51 and the comparator CP51.
The delay circuit DLY102 also comprises a ramp generator RG52, a comparator CP52, an inverter IV52, and a capacitive element C52. A signal line at the analog-output potential ANG51 is connected to the comparator CP51 and the comparator CP52. The ramp generator RG51 is connected to an input terminal DI51, the inverter IV52 is connected to an output terminal DO51, and the inverter IV51 is connected to the ramp generator RG52.
In the conventional variable delay circuit thus constituted, the delay circuit DLY101 of the first step delays the H.fwdarw.L edge of an input signal through the input terminal DI51 and the logic thereof is inverted by the inverter IV51. Next, the delay circuit DLY102 of the second step delays the H.fwdarw.L edge of the inverted signal, thereby delaying the L.fwdarw.H edge of the input signal through the input terminal DI51 in fact, and the logic thereof is inverted by the inverter IV52. The signal in which the H.fwdarw.L edge and L.fwdarw.H edge is delayed is supplied to the output terminal DO51. Generally, a delay circuit can only delay the H.fwdarw.L edge, which makes a signal inverted twice by the inverter IV51 and IV52 as mentioned above.
It is necessary to establish the analog-output potential ANG51 between the Lo level and Hi level output from the ramp generators RG51 and RG52, so as to invert the logic completely, with some margin enough to prevent from malfunction due to a noise. A delay setting signal is usually entered in digital form, and this digital signal is converted into an analog signal by a digital-to-analog converter (DAC: Digital-Analog Converter). In this case, since the analog signal will be varied accordingly to the change even if there is a change in the manufacturing process or power voltage, it is not necessary to consider any margin and the signal can be handled easily.
The conventional variable delay circuit, however, imposes a great restriction on the operating frequency in case of needing to achieve a high accuracy. This is why the proximity of L.fwdarw.H edge and H.fwdarw.L edge owing to the speed-up disturbs assurance of accuracy because the delay time is deviated by the effect of an overshoot. FIG. 19 is a timing chart showing a signal transferred within the conventional variable delay circuit. FIG. 20 is a graph showing the relationship therebetween with the analog output setting potential fixed as a horizontal axis and the delay time fixed as a vertical axis; FIG. 20(a) shows the H.fwdarw.L edge, and FIG. 20(b) shows the L.fwdarw.H edge. FIG. 21 is a graph showing the relationship therebetween with the analog output setting potential fixed as a horizontal axis and the duty ratio fixed as a vertical axis. In FIGS. 20(a) and (b) and FIG. 17, the analog output potential is lower at the right side.
In the above-mentioned conventional variable delay circuit, when the ramp generator RG51 receives L.fwdarw.H edge of a signal input through the input terminal DI51, the capacitive element C51 is immediately charged, with no generation of delay (node N51). The L.fwdarw.H edge is entered into the comparator CP51, L.fwdarw.H change occurs at the output side of the comparator CP51 (node N52). The edge is logically inverted by the inverter IV51 and the potential of the signal changes from H to L (node N53).
While, when the ramp generator RG51 receives H.fwdarw.L edge of a signal input through the input terminal DI51, the electric charge Q filled with the capacitive element C51 is gradually released by the constant-current power supply within the ramp generator RG51, thereby making a ramp waveform such as the potential gradually lowers (node N51). When the ramp waveform lowering at a constant gradient reaches the same potential as the analog output potential ANG51, the logic of the output of the comparator CP51 is inverted from H to L (node 52). Further, the edge is logically inverted by the inverter IV51 and the logic of the signal changes from L to H (node N53).
When the repeated waveform of L.fwdarw.H edge and H.fwdarw.L edge is entered into the input terminal DI51 and the signal output from the inverter IV51 is supplied to the delay circuit DLY102, the H.fwdarw.L edge is entered in the ramp generator RG52 during disturbance of the waveform at the L.fwdarw.H edge due to an overshoot. Therefore, discharge from the capacitive element C52 when the H.fwdarw.L linear waveform is entered in the ramp generator RG52 is started from the higher potential position or from the lower potential position than in the case where no overshoot occurs. Namely, the H.fwdarw.L linear waveform makes such a shape as moving in parallel vertically from the position where no overshoot occurs. Thus, the time when the H.fwdarw.L linear waveform reaches the same potential as the analog potential ANG51 is varied, thereby causing a change in the delay time as illustrated in FIGS. 20(a) and (b) and deteriorating the accuracy.
Since it is only at one edge that the delay time is varied by an overshoot, the duty ratio is varied according to the setting potential, as illustrated in FIG. 21. The L/H ratio of the output waveform of the delay circuit DLY101 is also varied according to the setting potential, thereby changing the influence of the overshoot in the delay circuit DLY102. This is the cause of deteriorating the linearity. It is a problem that the quality will be destroyed in order to speed up the performance.